Blogs

 

Entry Level Job Openings

Entry level job openings in Physical Design & Analog layout. Candidates from relevant branches are considered for the opening - Electronics, Electrical, VLSI, Digital Electronics “Our vision is to be a leading VLSI design service provider. Quality, Customer...

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UPF

Author : Dayanand Shambhu, Physical Design Engineer, SignOff Semiconductors, Power is one of the most concerned factor in the lower node technologies due to sophisticated operation of a system at higher frequencies, complex functionalities, wireless applications and...

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Post CTS Optimization

Author : Adhila A., Physical Design Engineer, SignOff Semiconductors, Author : Nisha K. P., Physical Design Engineer, SignOff Semiconductors During Clock tree synthesis, buffers or inverters are added in the clock nets to achieve minimum Insertion delay and Skew,...

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STA – Part1

Author : Nishant Lamani, Physical Design Engineer, SignOff Semiconductors, Author : Abhishek Kumar, Physical Design Engineer, SignOff Semiconductors What is STA ? Static timing analysis is one of the techniques used to verify the timing of a digital design. STA is...

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FinFET

Author : Nisha K. P., Physical Design Engineer, SignOff Semiconductors What are FinFETs? FinFETs are non-planar transistors built on SOI or Bulk substrate. FinFET describes any fin-based, multi-gate transistor architecture, regardless of the number of gates. The term...

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Pulse Width Reduction

Author : Srinivasu Rajanala, Physical Design Engineer, SignOff Semiconductors Please read our blog on cell design to implement clock buffer. What is the need of balanced buffers in clock path (Pulse Width Violation) ? Balanced buffers are preferred for clock tree...

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PVT, RC Variation & OCV

Author : Adhila A., Physical Design Engineer, SignOff Semiconductors, Author : Sumeet Anwikar, Physical Design Engineer, SignOff Semiconductors PVT: PVT is abbreviation for Process, Voltage and Temperature. In order to make our chip to work in all possible conditions,...

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SignOff checks

Author : Aglow A George, Physical Design Engineer, SignOff Semiconductors Author: Batchu Sri Sai Chaitanya, Physical Design Engineer, Signoff Semiconductors Author: Ashish Kumar Sharma, Physical Design Engineer, Signoff Semiconductors Design Rule Check (DRC) Design...

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LEF, DEF & LIB

Author: Ashish Kumar Sharma, Physical Design Engineer, Signoff Semiconductors Library Exchange Format (LEF) The LEF file is the abstract view of cells. It only gives the idea about PR boundary, pin position and metal layer information of a cell. To get the complete...

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Life @ SignOff

  “Our vision is to be a leading VLSI design service provider. Quality, Customer success & TTM are our key goals” “We never compromise on technical growth, developing right attitude & approach among engineers, strong work ethics, respect, care, concern...

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Synthesis

Author: Batchu Sri Sai Chaitanya, Physical Design Engineer, Signoff Semiconductors Synthesis is process of converting RTL (Synthesizable Verilog code) to technology specific gate level netlist (includes nets, sequential and combinational cells and their connectivity)....

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Standard Cell Library

Author : Aglow A George, Physical Design Engineer, SignOff Semiconductors Author : Nisha K. P., Physical Design Engineer, SignOff Semiconductors Standard Cell Architecture Standard cells are designed based on power, area and performance. First step is cell...

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Clock Tree Synthesis- part 1

Author : Nishant Lamani, Physical Design Engineer, SignOff Semiconductors Clock Tree Synthesis (CTS) is one of the most important stages in PnR. CTS QoR decides timing convergence & power. In most of the ICs clock consumes 30-40 % of total power. So efficient...

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Routing

Author: Avik Sumed Arun, Physical Design Engineer, SignOff Semiconductors Pvt Ltd Routing is the stage after Clock Tree Synthesis and optimization where- Exact paths for the interconnection of standard cells and macros and I/O pins are determined. Electrical...

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PD Flow I – Floorplan

PHYSICAL DESIGN – I (Import Design, Floorplan, Placement) Physical design is process of transforming netlist into layout which is manufacture-able [GDS]. Physical design process is often referred as PnR (Place and Route) / APR (Automatic Place & Route). Main steps...

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