Careers

We make our team feel respected, empowered and genuinely excited about the company’s mission

 

“Our vision is to be a leading VLSI design service provider. Quality, Customer success & TTM are our key goals”

“We never compromise on technical growth, developing right attitude & approach among engineers, strong work ethics, respect, care, concern and collective growth”

Gaurav Bansal, CEO SignOff Semiconductors Pvt Ltd.

Life at SignOff

  • Company is established with a genuine vision to solve key problems of the service industry.
  • Very well planned training sessions & priority given for individual growth makes it one of the best companies to start your career.
  • Transparency, respect are never compromised.
  • Regular one to one sessions & very transparent work environment. Fair decision is made on any concern/issues.
  • Company provides lot of perks, bonus, and quarterly outings.

Job openings

Physical Design Engineer I

Job description

Education : BTech in EC/EE/Telecommunication is must. MS/MTech VLSI is preferred

Location : Bangalore

No. of positions : 6


Desired Skills:

  • Minimum 1+ year of experience
  • Should have block/SOC level netlist-gds2 experience.
  • Expertise in Floorplaning, Power planning, CTS.
  • Should be capable of handling block-level timing closure.
  • Should have knowledge on all low power & signoff checks, like MVRC/CLP, LEC/Formality, DRC, LVS, IR, EM.
  • Good scripting skills (TCL / SHELL).
  • Experience on low power implementation techniques is preferred.
  • Synopsys/Cadence tool experience is preferred.
  • Good communication skills.

Interested candidates, please send your latest resume to hr@signoffsemi.com

Synthesis & STA

Job description

Education : BTech in EC/EE/Telecommunication is must. MS/MTech VLSI is preferred

Location : Bangalore

No. of positions : 2


Desired Skills:

  • Minimum 2+ year of experience in Synthesis and STA
  • Should have worked on several full chip designs both flat and hierarchical designs
  • Strong knowledge in RTL to Netlist handoff to Physical design team
  • Experience in low power/multi voltage design and understanding of UPF is preferred
  • Knowledge on Cadence based flows is preferred
  • Knowledge on DFT and Physical design is preferred
  • Synopsys/Cadence tool experience is preferred.
  • Good communication skills.

Interested candidates, please send your latest resume to hr@signoffsemi.com

Analog Layout Engineer I

Job description

Education : BTech in EC/EE/Telecommunication is must. MS/MTech VLSI is preferred

Location : Bangalore

No. of positions : 5


Desired Skills:

  • Minimum 2+ year of experience
  • Good understanding of CMOS and FinFet technologies (device physics, deep sub-micron effects, and layout effects)
  • Proficient in EDA tools used for layout design (e.g. Virtuoso/OA for layout design – L/XL/GXL, Calibre for DRC/LVS/DFM, StarRC/QRC for Extraction, tools for Electro-migration and IR Drop analysis)
  • Good understanding of Design Rule Manual and Design Rules
  • Good understanding of Analog Layout fundamentals (e.g. Matching, Electro-migration, Latch-up, coupling, cross-talk, IR-drop, active and passive parasitic devices etc.)
  • Ability to understand design constraints and implement high-quality layouts accordingly
  • Technical troubleshooting and demonstrated problem-solving skills
  • Team player, flexible, good communication skills
  • Good understanding of usage of standard cells in P & R and proficiency in P & R flow is desirable
  • Scripting language (SKILL/Perl/TCL) proficiency is also desirable
  • Provide reasonably accurate estimates of timescales for work
  • Solutions orientation; Quality driven; Execution minded; Customer focused
  • Good communication skills.

Interested candidates, please send your latest resume to hr@signoffsemi.com

Lead Physical Design Engineer

Job description

Education : BTech in EC/EE/Telecommunication is must. MS/MTech VLSI is preferred

Location : Bangalore

No. of positions : 3


Desired Skills:

  • Minimum 4+ year of experience
  • Should have block/SOC level netlist-gds2 experience.
  • Expertise in Floorplaning, Power planning, CTS.
  • Should be capable of handling block-level timing closure.
  • Should have knowledge on all low power & signoff checks, like MVRC/CLP, LEC/Formality, DRC, LVS, IR, EM.
  • Good scripting skills (TCL / SHELL).
  • Experience on low power implementation techniques is preferred.
  • Synopsys/Cadence tool experience is preferred.
  • Should be capable to lead a team of 5+ junior engineers. Should be able to provide any training/guidance that team members need
  • Bachelor degree in EC/EE is must or Mater degree in VLSI is preferred.
  • Good communication skills.

Interested candidates, please send your latest resume to hr@signoffsemi.com

Standard Cell Characterization

Job description

Education : BTech in EC/EE/Telecommunication is must. MS/MTech VLSI is preferred

Location : Bangalore

No. of positions : 2


Desired Skills:

  • Minimum 2+ year of experience in Synthesis and STA
  • Knowledge of the complete characterization flows, library validation and timing/power characterization methodologies for standard cells
  • Familiarity with Simulators, liberty syntax requirements, CCS, statistical characterization, Verilog models, STA and power analysis tools
  • Understanding issues related to advanced nanometer technologies like EM/IR, SI,LOD and proximity-effects
  • Scripting skills using TCL, Perl, Python and Cadence SKILL is a plus
  • Good communication skills.

Interested candidates, please send your latest resume to hr@signoffsemi.com

Lead Analog Layout Engineer

Job description

Education : BTech in EC/EE/Telecommunication is must. MS/MTech VLSI is preferred

Location : Bangalore

No. of positions : 2


Desired Skills:

  • Minimum 4+ year of experience
  • Good understanding of CMOS and FinFet technologies (device physics, deep sub-micron effects, and layout effects)
  • Proficient in EDA tools used for layout design (e.g. Virtuoso/OA for layout design – L/XL/GXL, Calibre for DRC/LVS/DFM, StarRC/QRC for Extraction, tools for Electro-migration and IR Drop analysis)
  • Good understanding of Design Rule Manual and Design Rules
  • Good understanding of Analog Layout fundamentals (e.g. Matching, Electro-migration, Latch-up, coupling, cross-talk, IR-drop, active and passive parasitic devices etc.)
  • Ability to understand design constraints and implement high-quality layouts accordingly
  • Technical troubleshooting and demonstrated problem-solving skills
  • Team player, flexible, good communication skills
  • Good understanding of usage of standard cells in P & R and proficiency in P & R flow is desirable
  • Scripting language (SKILL/Perl/TCL) proficiency is also desirable
  • Provide reasonably accurate estimates of timescales for work
  • Solutions orientation; Quality driven; Execution minded; Customer focused
  • Good communication skills.

Interested candidates, please send your latest resume to hr@signoffsemi.com